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256mb: x4, x8, x16 ddr2 sdram ? pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_1.fm - rev. c 7/06 en 1 ?2003 micron technology, inc. all rights reserved. ddr2 sdram saa64m4.....? 16 meg x 4 x 4 SAA32M8.....? 8 meg x 8 x 4 saa16m16.....? 4 meg x 16 x 4 for the latest data sheet, please refer to the spectek web site: http://www.spectek.com features ?rohs compliant v dd = +1.8v 0.1v, v dd q = +1.8v 0.1v jedec standard 1.8v i/o (sstl_18-compatible) differential data strobe (dqs, dqs#) option four-bit prefetch architecture dll to align dq and dqs transitions with ck four internal banks for concurrent operation programmable cas latency (cl): 3 and 4 posted cas additive latency (al): 0, 1, 2, 3, and 4 write latency = read latency - 1 t ck programmable burst lengths: 4 or 8 adjustable data-output drive strength 64ms, 8,192-cycle refresh on-die termination (odt) note: 1. see page 42 for part number options and desig- nations used prior to march 2005. 2. see page 42 for part number options and desig- nations used prior to july 2006. 3. contact spectek sales for details on availability of the "x" placeholders part number example: SAA32M8u26ao8fif-37e options 1, 2 designation spectek memory saa configuration 64 meg x 4 (16 meg x 4 x 4) 64m4 32 meg x 8 ( 8 meg x 8 x 4) 32m8 16 meg x 16 (4 meg x 16 x 4) 16m16 product code ddr2 ux 3 density 256 megabits 6x 3 voltage/refresh 1.8v/8k refresh o8 package ? lead-free x4, x8 60-ball fbga (8mm x 12mm) fif x16 84-ball fbga (8mm x 14mm) fpf package ? leaded x4, x8 60-ball fbga (8mm x 12mm) fil x16 84-ball fbga (8mm x 14mm) fpl timing ? cycle time 3.0ns @ cl = 5 (ddr2-667) -3 3.75ns @ cl = 4 (ddr2-533) -37e architecture 64 meg x 4 32 meg x 8 16 meg x 16 configuration 16 meg x 4 x 4 8 meg x 8 x 4 4 meg x 16 x 4 refresh count 8k 8k 8k row addressing 8k ( a0?a12 )8k ( a0?a12 )8k ( a0?a12 ) bank addressing 4 (ba0?ba1) 4 (ba0?ba1) 4 (ba0?ba1) column addressing 2k ( a0?a9, a11 )1k ( a0?a9 ) 512 ( a0?a8 ) table 1: key timing parameters speed grade data rate (mhz) t rcd (ns) t rp (ns) t rc (ns) cl = 4 cl = 5 -3 na667151560 -37e 533 533 15 15 60
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mbtoc.fm - rev. c 7/06 en 2 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 fbga part marking decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 ac and dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 input electrical characteristics and operat ing conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 input slew rate derating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 data slew rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 power and ground clamp characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 ac overshoot/undershoot specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 output electrical charac teristics and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 full strength pull-down driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 full strength pull-up driver characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 fbga package capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 i dd specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 i dd 7 conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 data sheet designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 part number options and designations prior to march 2005. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 part number options and designations prior to july 2006 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mblof.fm - rev. c 7/06 en 3 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? list of figures figure 1: 84-ball fbga pin assignment (x16), 8mm x 14mm (top vi ew) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 2: 60-ball fbga pin assignment (x 4, x 8), 8mm x 12mm (t op view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 3: functional block diagram (64 meg x 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 4: functional block diagram (32 meg x 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 5: functional block diagram (16 meg x 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 6: example temperature test point location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 7: single-ended input signal levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 8: differential input signal levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 9: nominal slew rate for t is . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 10: tangent line for t is . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 11: nominal slew rate for t ih. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 12: tangent line for t ih . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 13: nominal slew rate for t ds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 14: tangent line for t ds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 15: nominal slew rate for t dh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 16: tangent line for t dh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 17: ac input test signal waveform command/address pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 18: ac input test signal waveform for data with dqs,dqs# (differential) . . . . . . . . . . . . . . . . . . . . . . . .23 figure 19: ac input test signal waveform for data with dqs (sin gle-ended) . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 20: ac input test signal waveform (differential). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 21: input clamp characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 22: overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 23: undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 24: differential output signal levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 25: output slew rate load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 26: full strength pull-down characte ristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 27: full strength pull-up characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 28: package drawing 60-ball (8mm x 12mm) fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 29: package drawing 84-ball (8mm x 14mm) fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mblot.fm - rev. c 7/06 en 4 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? list of tables table 1: key timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: fbga ball descriptions 64 meg x 4, 32 meg x 8, 16 meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 table 3: absolute maximum dc ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 4: recommended dc operating conditions (sstl_18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 5: odt dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 6: input dc logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 7: input ac logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 8: differential input logic levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 table 9: ac input test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 10: setup and hold time derating values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 11: t ds, t dh derating values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 12: input clamp characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 13: address and control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 14: clock, data, strobe, and mask pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 15: differential ac output parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 16: output dc current drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 17: output characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 18: pulldown current (ma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 19: pull-up current (ma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 20: input capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 21: ddr2 i dd specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 22: general i dd parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 23: i dd 7 timing patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 24: ac operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 5 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? fbga part marking decoder due to space limitations, fbga-packaged compo- nents have an abbreviated part marking that is differ- ent from the part number. spectek?s new fbga part marking decoder makes it easier to understand fbga part marking. visit the spectek web site at www.spec- tek.com/pdfs/fbga_decoder.pdf . general description the 256mb ddr2 sdram is a high-speed, cmos dynamic random-access memory containing 268,435,456 bits. it is internally configured as a quad- bank dram. the functional block diagrams of the 16 meg x 16, 32 meg x 8, and 64 meg x 4 devices, respec- tively are shown in the func tional description section. ball assignments for the 64 meg x 4 are shown in figure 1 and signal descriptions are shown in table 1. ball assignments for the 32 meg x 8 and 64 meg x 4 are shown in figure 2 and signal descriptions are shown in tabl e 2. the 256mb ddr2 sdram uses a double data rate architecture to achieve high-speed operation. the double data rate architec ture is essentially a 4 n - prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 256mb ddr2 sdram effectively consists of a single 4 n -bit-wide, one-clock-cycle data transf er at the internal dram core and four corresponding n -bit-wide, one-half- clock-cycle data transfers at the i/o pins. a bidirectional data strobe (dqs, dqs#) is transmit- ted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr2 sdram during reads and by the memory con- troller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. the x16 offering has two data strobes, one for the lower byte (ldqs, ldqs#) and one for the upper byte (udqs, udqs#). the 256mb ddr2 sdram operates from a differen- tial clock (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. commands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. read and write accesses to the ddr2 sdram are burst-oriented; accesses st art at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then fol- lowed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access. the ddr2 sdram provides for programmable read or write burst lengths of four or eight locations. ddr2 sdram supports interrupting a burst read of eight with another read, or a burst write of eight with another write. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. as with standard ddr sdrams, the pipelined, multibank architecture of ddr2 sdrams allows for concurrent operation, ther eby providing high, effec- tive bandwidth by hiding row precharge and activation time. a self refresh mode is provided, along with a power- saving power-down mode. all inputs are compatible with the jedec standard for sstl_18. all full drive-strength outputs are sstl_18-compatible. note: 1. the functionality and the timing specifica- tions discussed in this data sheet are for the dll-enabled mode of operation. 2. throughout the data sheet, the various fig- ures and text refer to dqs as ?dq.? the dq term is to be interpreted as any and all dq collectively, unless specifically stated other- wise. additionally, the x16 is divided into two bytes, the lower byte and upper byte. for the lower byte (dq0 through dq7) dm refers to ldm and dqs refers to ldqs. for the upper byte (dq8 through dq15) dm refers to udm and dqs refers to udqs. 3. complete functionality is described throughout the document and any page or diagram may have been simplified to con- vey a topic and may not be inclusive of all requirements. 4. any specific requirement takes precedence over a general statement.
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 6 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? figure 1: 84-ball fbga pin assignment (x16), 8mm x 14mm (top view) figure 2: 60-ball fbga pin assignment (x 4, x 8), 8mm x 12mm (top view) 1234 6789 5 v dd dq14 v dd q dq12 v dd dq6 v dd q dq4 v dd l rfu v ss v dd nc v ss q dq9 v ss q nc v ss q dq1 v ss q vref cke ba0 a10 a3 a7 a12 v ss udm v dd q dq11 v ss ldm v dd q dq3 v ss we# ba1 a1 a5 a9 rfu v ss q udqs v dd q dq10 v ss q ldqs v dd q dq2 v ss dl ras# cas# a2 a6 a11 rfu v dd q dq15 v dd q dq13 v dd q dq7 v dd q dq5 v dd odt v dd v ss nu/udqs# v ss q dq8 v ss q nu/ldqs# v ss q dq0 v ss q ck ck# cs# a0 a4 a8 rfu a b c d e f g h j k l m n p r 1234 6789 5 a b c d e f g h j k l v dd nf,dq6 v dd q nf,dq4 v dd l rfu v ss v dd nc,nu/rdqs# v ss q dq1 v ss q vref cke ba0 a10 a3 a7 a12 nu/dqs# v ss q dq0 v ss q ck ck# cs# a0 a4 a8 rfu v ss dm,dm/rdqs v dd q dq3 v ss we# ba1 a1 a5 a9 rfu v ss q dqs v dd q dq2 v ss dl ras# cas# a2 a6 a11 rfu v dd q nf,dq7 v dd q nf,dq5 v dd odt v dd v ss
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 7 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? table 2: fbga ball descriptions 64 me g x 4, 32 meg x 8, 16 meg x 16 x16 fbga ball assignment x4, x8 fbga ball assignment symbol type description k9 f9 odt input on-die termination: odt (registe red high) enables termination resistance internal to the ddr2 sd ram. when enabled, odt is only applied to each of the following pins: dq0?dq15, ldm, udm, ldqs, ldqs#, udqs, and udqs# for the x16; dq0-dq 7, dqs, dqs#, rdqs, rdqs#, and dm for the x8 ; dq0-dq3, dqs, dqs#, and dm for the x4. the odt input will be ig nored if disabled via the load mode command. j8, k8 e8, f8 ck, ck# input clock: ck and ck# are differenti al clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck#. output data (dqs and dqs/ dqs#) is referenced to the crossings of ck and ck#. k2 f2 cke input clock enable: cke (registered high) activates and cke (registered low) deactivates cloc king circuitry on the ddr2 sdram. the specific circuitry that is enabled/ disabled is dependent on the ddr2 sdram configuration and operating mode. cke low provides precharge power-down and self refresh operations (all banks idle), or active power-down (row active in any bank). cke is synchronous for power-down en try, power-down exit, output disable, and for self refresh entr y. cke is asynchronous for self refresh exit. input buffers (excludi ng ck, ck#, cke, and odt) are disabled during power-down. input buffers (excluding cke) are disabled during self refresh. cke is an sstl_18 input but will detect a lvcmos low level once vdd is applied during first power- up. after vref has become stable during the power on and initialization sequence, it must be maintained for proper operation of the cke receiver. for prop er self-refresh operation v ref must be maintained. l8 g8 cs# input chip select: cs# enables (registere d low) and disables (registered high) the command decoder. all commands are masked when cs# is registered high. cs# provides for external bank selection on systems with multiple ranks. cs# is considered part of the command code. k7, l7, k3 f7, g7, f3 ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with cs#) define the command being entered. f3, b3 b3 ldm, udm input input data mask: dm is an input mask signal for write data. input data is masked when dm is samp led high along with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input-only, the dm loading is designed to match that of dq and dqs pins. ldm is dm for lower byte dq0? dq7 and udm is dm fo r upper byte dq8?dq15. l2, l3 g2, g3 ba0, ba1 input bank address inputs: ba0 and ba1 de fine to which bank an active, read, write, or precharge command is being applied. ba0 and ba1 define which mode register including mr, emr, emr(2), and emr(3) is loaded during the load mode command.
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 8 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? m8, m3, m7, n2, n8, n3, n7, p2, p8, p3, m2, p7, r2 h8, h3, h7, j2, j8, j3, j7, k2, k8, k3, h2, k7, l2 a0?a12 input address inputs: provide the row ad dress for active commands, and the column address and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge command determines whether the precharge applies to one bank (a10 low, bank selected by ba0, ba1) or all banks (a10 high). the address inputs also provide the op-code during a load mode command. g8, g2, h7, h3, h1, h9, f1, f9, c8, c2, d7, d3, d1, d9, b1, b9 ?dq0? dq15 i/o data input/output: bidirectio nal data bus for 16 meg x 16. ? c8, c2, d7, d3, d1, d9, b1, b9 dq0?dq7 i/o data input/output: bidirectional data bus for 32 meg x 8. ? c8, c2, d7, d3 dq0?dq3 i/o data input/output: bidirectional data bus for 64 meg x 4. b7, a8 ? udqs, udqs# i/o data strobe for upper byte: outp ut with read data, input with write data for source synchronou s operation. edge-aligned with read data, center-aligned with write data. udqs# is only used when differential data s trobe mode is enabled via the load mode command. f7, e8 ? ldqs, ldqs# i/o data strobe for lower byte: outp ut with read data, input with write data for source synchronou s operation. edge-aligned with read data, center-aligned with write data. ldqs# is only used when differential data s trobe mode is enabled via the load mode command. ? b7, a8 dqs, dqs# i/o data strobe: output with read data, input with write data for source synchronous operation. ed ge-aligned with read data, center aligned with write data. dqs# is only used when differential data strobe mode is enabled vi a the load mode command. ? b3, a2 rdqs, rdqs# output redundant data strobe for 32 meg x 8 only. rdqs is enabled/ disabled via the load mode co mmand to the extended mode register (emr). when rdqs is enabled, rdqs is output with read data only and is ignored during wr ite data. when rdqs is disabled, pin b3 becomes data mask (see dm pin). rdqs# is only used when rdqs is enabled and differential data strobe mode is enabled. a1, e1, j9, m9, r1 a1, e9, h9, l1 v dd supply power supply: 1.8v 0.1v j1 e1 v dd l supply dll power supply: 1.8v 0.1v a9, c1, c3, c7, c9, e9, g1, g3, g7, g9 a9, c1, c3, c7, c9 v dd q supply dq power supply: 1.8v 0.1v. isolated on the device for improved noise immunity. j2 e2 v ref supply sstl_18 reference voltage. a3, e3, j3, n1, p9 a3, e3, j1, k9 v ss supply ground. j7 e7 v ss dl supply dll ground. isolated on the device from v ss and v ss q. a7, b2, b8, d2, d8, e7, f2, f8, h2, h8, a7, b2, b8, d2, d8 v ss q supply dq ground. isolated on the device for improved noise immunity. table 2: fbga ball descriptions 64 me g x 4, 32 meg x 8, 16 meg x 16 x16 fbga ball assignment x4, x8 fbga ball assignment symbol type description
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 9 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? a2, e2 a2, b1, b9, d1, d9 nc ? no connect: these pins should be left unconnected. d1, d9, b1, b9 nf - no function: these pins are used as dq4-dq7 on the 32 meg x 8, but are nf (no function) on the 16 meg x 16 configuration. a8, e8 a2, a8 nu ? not used: if emr[e10] = 0, a8 and e8 are udqs# and ldqs#. if emr[e10] = 1, then a8 and e8 are not used. l1, r3, r7, r8 g1, l3, l7, l8 rfu ? reserved for future use; bank addr ess bit ba2(l1) for 1gb, 2gb, and 4gb densities. row address bits a13(r8), a14(r3) and a15(r7) for higher densities. table 2: fbga ball descriptions 64 me g x 4, 32 meg x 8, 16 meg x 16 x16 fbga ball assignment x4, x8 fbga ball assignment symbol type description
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 10 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? functional description the 256mb ddr2 sdram is a high-speed, cmos dynamic random-access memory containing 268,435,456 bits. the 256mb ddr2 sdram is inter- nally configured as a four-bank dram. the 256mb ddr2 sdram uses a double data rate architecture to achieve high-speed operation. the ddr2 architecture is essentially a 4 n -prefetch archi- tecture, with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 256mb ddr2 sdram consists of a single 4 n -bit-wide, one-clock-cycle data transfer at the internal dram core and four corresponding n -bit- wide, one-half-clock-cycle data transfers at the i/o pins. prior to normal operation, the ddr2 sdram must be initialized. the following sections provide detailed information covering device initialization, register def- inition, command descriptions, and device operation. figure 3: functional block diagram (64 meg x 4) 13 ras# cas# row- address mux ck cs# we# ck# control logic column- address counter/ latch mode registers 11 command decode a0-a12, ba0, ba1 cke 13 address register 15 512 (x16) 8,192 i/o gating dm mask logic column decoder bank0 memory array (8,192 x 512 x 16) bank0 row- address latch & decoder 8,192 sense amplifiers bank control logic 15 bank1 bank2 bank3 13 9 2 2 refresh counter 4 4 4 2 rcvrs 16 16 16 ck out data dqs, dqs# ck, ck# col0,col1 col0,col1 ck in drvrs dll mux dqs generator 4 4 4 4 4 dq0?dq3 dqs, dqs# 2 read latch write fifo & drivers data 4 4 4 4 16 1 1 1 1 mask 1 1 1 1 1 4 4 4 2 bank1 bank2 bank3 input registers dm v dd q r1 r1 r2 r2 sw1 sw2 vssq r1 r1 r2 r2 sw1 sw2 r1 r1 r2 r2 sw1 sw2 odt sw1 sw2 odt control internal ck, ck#
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 11 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? figure 4: functional block diagram (32 meg x 8) figure 5: functional bl ock diagram (16 meg x 16) 13 row- address mux control logic column- address counter/ latch mode registers 10 command decode a0?a12, ba0, ba1 13 address register 15 256 (x32) 8,192 i/o gating dm mask logic column decoder bank0 memory array (8,192 x 256 x 32) bank0 row- address latch & decoder 8,192 sense amplifiers bank control logic 15 bank1 bank2 bank3 13 8 2 2 refresh counter 8 8 8 2 rcvrs 32 32 32 ck out data dqs, dqs# internal ck, ck# ck,ck# col0,col1 col0,col1 ck in drvrs dll mux dqs generator 8 8 8 8 8 dq0?dq7 dqs, dqs# 2 read latch write fifo & drivers data 8 8 8 8 32 1 1 1 1 mask 1 1 1 1 1 4 8 8 2 bank1 bank2 bank3 input registers dm rdqs# v dd q r1 r1 r2 r2 sw1 sw2 vssq r1 r1 r2 r2 sw1 sw2 r1 r1 r2 r2 sw1 sw2 sw1 sw2 odt control ras# cas# ck cs# we# ck# cke odt rdqs 13 row- address mux control logic column- address counter/ latch mode registers 9 a0?a12, ba0, ba1 13 address register 15 128 (x64) 8,192 i/o gating dm mask logic column decoder bank0 memory array (8,192 x 128 x 64) bank0 row- address latch & decoder 8,192 sense amplifiers bank control logic 15 bank1 bank2 bank3 13 7 2 2 refresh counter 16 16 16 4 rcvrs 64 64 64 ck out data udqs, udqs# ldqs, ldqs# internal ck, ck# ck,ck# col0,col1 col0,col1 ck in dll mux dqs generator 16 16 16 16 16 udqs, udqs# ldqs, ldqs# 4 read latch write fifo & drivers data 16 16 16 16 64 2 2 2 2 mask 2 2 2 2 2 8 16 16 2 bank1 bank2 bank3 input registers udm, ldm dq0?dq15 v dd q r1 r1 r2 r2 sw1 sw2 vssq r1 r1 r2 r2 sw1 sw2 r1 r1 r2 r2 sw1 sw2 sw1 sw2 odt control ras# cas# ck cs# we# ck# command decode cke odt drvrs
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 12 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? absolute maximum ratings stresses greater than those listed may cause perma- nent damage to the device. th is is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. figure 6: example temper ature test point location table 3: absolute maximum dc ratings symbol parameter min max units v dd v dd supply voltage relative to v ss -1.0 2.3 v v dd q v dd q supply voltage relative to v ss q -0.5 2.3 v v dd l v dd l supply voltage relative to vssl -0.5 2.3 v v in , v out voltage on any pin relative to v ss -0.5 2.3 v t stg storage temperature (t case ) 1 -55 100 c t c operating temperature (t case ) 1, 2 070c i i input leakage current any input 0v v in v dd (all other pins not under test = 0v) -5 5 a i oz output leakage current 0v v out v dd q dqs and odt are disabled -5 5 a i v ref v ref leakage current v ref = valid v ref level -2 2 a note: 1. max operating case temperature; t c is measured in the center of the package illustrated in figure 6. 2. device functionality is no t guaranteed if the dram de vice exceeds the maximum t c during operation. 8.00 4.00 12.00 6.00 test point 8mm x 12mm ?fi? fbga 8.00 4.00 14.00 7.00 8mm x 14mm ?fp? fbga
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 13 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? ac and dc operating conditions note: 1. v dd and v dd q must track each other. v dd q must be less than or equal to v dd . 2. v ref is expected to equal v dd q/2 of the transmitting device and to track vari ations in the dc level of the same. peak-to- peak noise (non-common mode) on v ref may not exceed 1% of the dc value. peak-to-peak ac noise on v ref may not exceed 2 percent of v ref ( dc ). this measurement is to be taken at the nearest v ref bypass capacitor. 3. v tt is not applied directly to the device. v tt is a system supply for sign al termination resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref . 4. v dd q tracks with v dd ; v dd l tracks with v dd . 5. vssq = vssl = vss note: 1. r tt 1( eff ) and r tt 2( eff ) are determined by applying v ih ( ac ) and v il ( ac ) to pin under test separately, then measure current i(v ih ( ac )) and i(v il ( ac )) respectively. 2. measure voltage (vm) at tested pin with no load. table 4: recommended dc op erating conditions (sstl_18) all voltages referenced to v ss parameter symbol min nom max units notes supply voltage v dd 1.7 1.8 1.9 v 1, 5 v dd l supply voltage v dd l 1.7 1.8 1.9 v 4, 5 i/o supply voltage v dd q 1.7 1.8 1.9 v 4, 5 i/o reference voltage v ref ( dc ) 0.49 x v dd q 0.50 x v dd q 0.51 x v dd qv 2 i/o termination voltage (system) v tt v ref ( dc ) - 40 v ref ( dc )v ref ( dc ) + 40 mv 3 table 5: odt dc electrical characteristics all voltages referenced to v ss parameter symbol min nom max units notes r tt effective impedance value for 75 ? setting emr (a6, a2) = 0, 1 r tt 1( eff )60 75 90 ? 1 r tt effective impedance value for 150 ? setting emr (a6, a2) = 1, 0 r tt 2( eff ) 120 150 180 ? 1 deviation of vm with respect to v dd q/2 ? vm -6% 6% % 2 r tt eff () v ih ac () v il ac () ? iv ih ac () () iv il ac () () ? -------------------- --------------------- -------------------- = ? vm 2 vm v dd q ----------------- - 1 ? ?? ?? 100% =
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 14 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? input electrical characteris tics and operating conditions figure 7: single-end ed input signal levels note: numbers in diagram reflect nomimal values. table 6: input dc logic levels all voltages referenced to v ss parameter symbol min max units notes input high (logic 1) voltage v ih ( dc )v ref ( dc ) + 125 v dd q + 300 mv input low (logic 0) voltage v il ( dc ) -300 v ref ( dc ) - 125 mv table 7: input ac logic levels all voltages referenced to v ss parameter symbol min max units notes input high (logic 1) voltage v ih ( ac )v ref ( dc ) + 250 - mv input low (logic 0) voltage v il ( ac )? v ref ( dc ) - 250 mv 650mv 775mv 864mv 882mv 900mv 918mv 936mv 1,025mv 1,150mv v il (ac) v il (dc) v ref - ac noise v ref - dc error v ref + dc error v ref + ac noise v ih (dc) v ih (ac)
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 15 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? note: 1. v in (dc) specifies the allowable dc execution of each input of differential pair such as ck, ck#, dqs, dqs#, ldqs, ldqs#, udqs, udqs#, and rdqs, rdqs#. 2. v id (dc) specifies the input differential voltage | v tr - v cp | required for switching, where v tr is the true input (such as ck, dqs, ldqs, udqs, rdqs) level and v cp is the complementary input (such as ck#, dqs#, ldqs#, udqs#, rdqs#). the minimum value is equal to v ih (dc) - v il (dc). differential input signal levels are shown in figure 8. 3. v id (ac) specifies the input differential voltage | v tr - v cp | required for switching, where v tr is the true input (such as ck, dqs, ldqs, udqs, rdqs) level and v cp is the complementary input (such as ck#, dqs#, ldqs#, udqs#, rdqs#). the minimum value is equal to v ih (ac) - v il (ac) from table 7 on page 14. 4. the typical value of v ix (ac) is expected to be about 0.5 x v dd q of the transmitting device and v ix (ac) is expected to track variations in v dd q. v ix (ac) indicates the voltage at which differen tial input sign als must cross as shown in figure 8. 5. v mp ( dc ) specifies the input differen tial common mode voltage (v tr + v cp )/2 where v tr is the true input (ck, dqs) level and v cp is the complementary input (ck#, dqs#). v mp ( dc ) is expected to be about 0.5*v dd q. figure 8: differenti al input signal levels note: 1. this provides a minimum of 850mv to a ma ximum of 950mv and is expected to be v dd q/2. 2. tr and cp must cross in this region. 3. tr and cp must meet at least v id (dc) min when static and is centered around v mp (dc). 4. tr and cp must have a mi nimum 500mv peak-to-peak swing. 5. tr and cp may not be more positive than v dd q + 0.3v or more negative than v ss - 0.3v. 6. for ac operation, all dc clock re quirements must also be satisfied. 7. numbers in diagram reflect nominal values. 8. tr represents the ck, dqs, rdqs, ldqs and udqs signals; cp represents ck#, dqs#, rdqs#, ldqs# and udqs# signals. table 8: differential input logic levels all voltages referenced to v ss parameter symbol min max units notes dc input signal voltage v in (dc) -300 v dd q + 300 mv 1 dc differential input voltage v id (dc) 250 v dd q + 600 mv 2 ac differential input voltage v id (ac) 500 v dd q + 600 mv 3 ac differential cross-point voltage v ix (ac) 0.50 x v dd q - 175 0.50 x v dd q + 175 mv 4 input midpoint voltage v mp ( dc ) 850 950 mv 5 cp 8 tr 8 2.1 v @ v dd q=1.8v 2 3 v in(dc) max 5 v in(dc) min 5 4 - 0.30v 0.9v 1.075 v 0.725 v v id (ac) v id (dc) x 1 v mp (dc) v ix (ac) x
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 16 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? note: 1. all voltages referenced to v ss . 2. input waveform setup timing ( t is b ) is referenced from the inpu t signal crossi ng at the v ih(ac) level for a risi ng signal and v il ( dc ) for a falling signal applied to the de vice under test as shown in figure 17. 3. input waveform hold ( t ih b ) timing is referenced from the input signal cro ssing at the v il ( dc ) level for a rising signal and v ih ( dc ) for a falling signal appl ied to the device under test as shown in figure 17 4. input waveform setup timing ( t ds) and hold timing ( t dh) for single-ended data strobe is referenced from the crossing of dqs, udqs, or ldqs through the v ref level applied to the device under test as shown in figure 19. 5. input waveform setup timing ( t ds) and hold timing ( t dh) when differential data strobe is enabled is referenced from the crosspoint of dqs,dqs# or udqs,udqs# or ldqs,ldq s# as shown in figure 18. 6. input waveform ti ming is referenced to th e crossing point level (v ix ) of two input signals (v tr and v cp ) applied to the device under test, where v tr is the ?true? in put signal and v cp is the ?complementary? inpu t signal shown in figure 20. 7. see ?input slew rate derating? on page 17. table 9: ac input test conditions parameter symbol min max units notes input setup timing measurement reference level ba1-ba0, a0-a12, cs#, ra s#, cas#, we#, odt, dm, udm, ldm and cke v rs see note 2 1, 2, input hold timing meas urement reference level ba1-ba0, a0-a12, cs#, ra s#, cas#, we#, odt, dm, udm, ldm and cke v rh see note3 1, 3, input timing measurement refe rence level (single-ended) dqs for x4x8; udqs, ldqs for x16 v ref ( dc )v dd q*0.49 v dd q*0.51 v 1, 4 input timing measurement re ference level (differential) ck, ck# for x4,x8,x16 dqs, dqs# for x4,x8; rdqs, rdqs# for x8 udqs, udqs#, ldqs, ldqs# for x16 v rd v ix ( ac ) v 1, 5, 6
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 17 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? input slew rate derating for all input signals the total t is (setup time) and t ih (hold time) required is calc ulated by adding the data sheet t is(base) and t ih(base) value to the ? t is and ? t ih derating value respectively. example: t is (total setup time) = t is(base) + ? t is setup ( t is) nominal slew rate for a rising signal is defined as the slew rate be tween the last crossing of v ref ( dc ) and the first crossing of v ih ( ac )min. setup ( t is) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref (d c ) and the first crossing of v il (a c ) max . if the actual signal is always earlier than the nominal slew rate line between shaded ?v ref (d c ) to ac region?, use nominal slew rate for derating value (figure 9 on page 18) if the actual signal is later than the nomi nal slew rate line anywhere between shaded ?v ref (d c ) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (figure 10 on page 18) hold ( t ih) nominal slew rate for a rising signal is defined as the slew rate be tween the last crossing of v il ( dc ) max and the first crossing of v ref (d c ). hold ( t ih) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ih ( dc ) min and the first cr ossing of v ref (d c ). if the actual signal is always later than the nomina l slew rate line between shaded ?dc to v ref ( dc ) region?, use nominal slew rate for derating value (figure 11 on page 19) if the actual signal is earlier than the nominal slew rate line any- where between shaded ?dc to v ref ( dc ) region?, the slew rate of a tangent line to the actual signal from the dc level to v ref ( dc ) level is used for derating value (figure 12 on page 19) although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached v ih / il ( ac ) at the time of the rising clock tran- sition) a valid input signal is still required to complete the transition and reach v ih / il ( ac )). for slew rates in between the values listed in table 10, the derating valu es may obtained by linear interpolation. table 10: setup and hold time derating values ck,ck# differential slew rate 2.0 v/ns 1.5 v/ns 1.0 v/ns ? t is ? t ih ? t is ? t ih ? t is ? t ih units command/ address slew rate (v/ns) 4.0 +187 +94 +217 +124 +247 +154 ps 3.5 +179 +89 +209 +119 +239 +149 ps 3.0 +167 +83 +197 +113 +227 +143 ps 2.5 +150 +75 +180 +105 +210 +135 ps 2.0 +125 +45 +155 +75 +185 +105 ps 1.5 +83 +21 +113 +51 +143 +81 ps 1.0 0 0 +30 +30 +60 +60 ps 0.9 -11 -14 +19 +16 +49 +46 ps 0.8 -25 -31 +5 -1 +35 +29 ps 0.7 -43 -54 -13 -24 +17 +6 ps 0.6 -67 -83 -37 -53 -7 -23 ps 0.5 -110 -125 -80 -95 -50 -65 ps 0.4 -175 -188 -145 -158 -115 -128 ps 0.3 -285 -292 -255 -262 -225 -232 ps 0.25 -350 -375 -320 -345 -290 -315 ps 0.2 -525 -500 -495 -470 -465 -440 ps 0.15 -800 -708 -770 -678 -740 -648 ps 0.1 -1450 -1125 -1420 -1095 -1390 -1065 ps
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 18 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? figure 9: nomina l slew rate for t is figure 10: tangent line for t is v ss ck ck tih tis tih setup slew rate setup slew rate rising signal falling signal delta tf delta tr v ref(dc) - vil(ac)max delta tf = vih(ac)min - v ref(dc) delta tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tis nominal slew rate nominal slew rate vref to ac region vref to ac region v ss ck ck tih tis tih setup slew rate rising signal delta tf delta tr tangent line[vih(ac)min - v ref(dc) ] delta tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tis tangent tangent v ref to ac region v ref to ac region line line nominal line nominal line
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 19 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? figure 11: nominal slew rate for t ih figure 12: tangent line for t ih v ss ck ck tih tis tih delta tr delta tf v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tis nominal slew rate nominal slew rate dc to v ref region dc to v ref region v ss ck ck tih tis tih hold slew rate delta tf delta tr tangent line [ vih(dc)min - v ref(dc) ] delta tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tis tangent tangent dc to v ref region dc to v ref region line line nominal line nominal line falling signal hold slew rate tangent line [ v ref(dc) - vil(dc)max ] delta tr = rising signal
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 20 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? data slew rating note: 1. for all input signals the total t ds (setup time) and t dh (hold time) required is calculat ed by adding the datasheet value to the derating value listed in table 11. 2. setup ( t ds) nominal slew rate for a rising signal is define d as the slew rate between the last crossing of v ref(dc) and the first crossing of vih(ac)min. setup ( t ds) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of vil(ac)max. if the actual signal is always earlier th an the nomina l slew rate line between shaded ?v ref(dc) to ac region?, use nominal slew rate for derati ng value (see figure 13) if the actual signal is later than the nominal slew rate line anywhere between shaded ?v ref(dc) to ac region?, the slew rate of a tangent line to the actual signal fro m the ac level to dc level is us ed for derating value (see figure 14) 3. hold ( t dh) nominal slew rate for a rising sign al is defined as the slew rate betwee n the last crossing of vil(dc)max and the first crossing of v ref(dc) . hold ( t dh) nominal slew rate for a fa lling signal is defined as th e slew rate between the last crossing of vih(dc)min and the first crossing of v ref(dc) . if the actual signal is always la ter than the nominal slew rate line between shaded ?dc level to v ref(dc) region?, use nominal slew rate for derating value (see figu re 15) if the actual signal is earlier than the nomina l slew rate line anywhere between shaded ?dc to v ref(dc) region?, the slew rate of a tangent line to the actual signal from the dc level to v ref(dc) level is used for derating value (see figure 16) 4. although for slow slew rates the total setup time might be negative (i.e. a va lid input signal will not have reached v ih/ il (ac) at the time of the rising clock trans ition) a valid input signal is still requ ired to complete th e transition and reach v ih/il (ac). 5. for slew rates in between the values listed in table 11, the derating values may obtain ed by linear interpolation. 6. these values are typically not subjec t to production test. they are veri fied by design and characterization. table 11: t ds, t dh derating values note 1; all units in ps dqs,dqs# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4v/ns 1.2v/ns 1.0v/ns 0.8v/ns ? t ds ? t d h ? t d s ? t d h ? t d s ? t d h ? t d s ? t d h ? t d s ? t d h ? t d s ? t d h ? t d s ? t d h ? t d s ? t d h ? t d s ? t d h dq slew rate v/ns 2.0125451254512545------------ 1.58321832183219533---------- 1.000000012122424-------- 0.9---11-14-11-141-213102522------ 0.8 - - - - -25 -31 -13 -19 -1 -7 11 5 23 17 - - - - 0.7 - - - - - - -31 -42 -19 -30 -7 -18 5 -6 17 6 - - 0.6 - - - - - - - - -43 -59 -31 -47 -19 -35 -7 -23 5 -11 0.5 - - - - - - - - - - -74 -89 -62 -77 -50 -65 -38 -53 0.4----- - -------127-140-115-128-103-116
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 21 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? figure 13: nominal slew rate for t ds figure 14: tangent line for t ds v ss dqs note1 dqs note1 tdh tds tdh setup slew rate setup slew rate rising signal falling signal delta tf delta tr v ref(dc) - vil(ac)max delta tf = vih(ac)min - v ref(dc) delta tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tds nominal slew rate nominal slew rate vref to ac region vref to ac region note1 dqs, dqs# signals must be monotonic between vil(dc)max and vih(dc)min. v ss dqs note1 dqs note1 tdh tds tdh setup slew rate setup slew rate rising signal falling signal delta tf delta tr tangent line[ v ref(dc) - vil(ac)max] delta tf = tangent line[vih(ac)min - v ref(dc) ] delta tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tds tangent tangent v ref to ac region v ref to ac region line line nominal line nominal line note1 dqs, dqs# signals must be monotonic between vil(dc)max and vih(dc)min.
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 22 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? figure 15: nominal slew rate for t dh figure 16: tangent line for t dh v ss dqs note1 dqs note1 tdh tds tdh hold slew rate hold slew rate falling signal rising signal delta tr delta tf v ref(dc) - vil(dc)max delta tr = vih(dc)min - v ref(dc) delta tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tds nominal slew rate nominal slew rate dc to v ref region dc to v ref region note1 dqs, dqs# signals must be monotonic between vil(dc)max and vih(dc)min. v ss dqs note1 dqs note1 tdh tds tdh hold slew rate delta tf delta tr tangent line [ vih(dc)min - v ref(dc) ] delta tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tds tangent tangent dc to v ref region dc to v ref region line line nominal line nominal line falling signal hold slew rate tangent line [ v ref(dc) - vil(dc)max ] delta tr = rising signal note1 dqs, dqs# signals must be monotonic between vil(dc)max and vih(dc)min.
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 23 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? figure 17: ac input test si gnal waveform command/address pins figure 18: ac input test signal wavef orm for data with dq s,dqs# (differential) v ref (dc) v il (dc) ma x v il (ac) ma x v ss q v ih (dc) m in v ih (ac) mi n v dd q v swing (max) t is a l ogic levels v ref levels t ih a t is a t ih a t is b t ih b t is b t ih b ck# ck v ref (dc) v il (dc) ma x v il (ac) ma x v ss q v ih (dc) m in v ih (ac) mi n v dd q v swing (max) dqs# dqs t ds a t dh a t ds a t dh a t ds b t dh b t ds b t dh b l ogic levels v ref levels
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 24 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? figure 19: ac input test signal w aveform for data with dqs (single-ended) figure 20: ac input test si gnal waveform (differential) v ref (dc) v il (dc) ma x v il (ac) ma x v ss q v ih (dc) m in v ih (ac) mi n v dd q v swing (max) dqs v ref l ogic levels v ref levels v ref levels t ds a t dh a t ds a t dh a t ds b t dh b t ds b t dh b v tr v swing v cp v dd q v ss q v ix crossing point
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 25 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? power and ground clamp characteristics power and ground clamps are provided on the fol- lowing input-only pins: ba1-ba0, a0-a12, cs#, ras#, cas#, we#, odt, and cke. figure 21: input clamp characteristics table 12: input clamp characteristics voltage across clamp (v) minimum power clamp current (ma) minimum ground clamp current (ma) 0.0 0.0 0.0 0.1 0.0 0.0 0.2 0.0 0.0 0.3 0.0 0.0 0.4 0.0 0.0 0.5 0.0 0.0 0.6 0.0 0.0 0.7 0.0 0.0 0.8 0.1 0.1 0.9 1.0 1.0 1.0 2.5 2.5 1.1 4.7 4.7 1.2 6.8 6.8 1.3 9.1 9.1 1.4 11.0 11.0 1.5 13.5 13.5 1.6 16.0 16.0 1.7 18.2 18.2 1.8 21.0 21.0 0.0 5.0 10.0 15.0 20.0 25.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 voltage across clamp (v) minimum clamp current (ma)
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 26 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? ac overshoot/undershoot specification figure 22: overshoot figure 23: undershoot table 13: address and control pins applies to ba1-ba0, a0-a12, cs #, ras#, cas#, we#, cke, odt parameter specification -3 -37e maximum peak amplitude allowed for overshoot area (see figure 22) 0.9v 0.9v maximum peak amplitude allowed for undershoot area (see figure 23) 0.9v 0.9v maximum overshoot area above v dd (see figure 22) 0.75v-ns 0.56v-ns maximum undershoot area below v ss (see figure 23) 0.75v-ns 0.56v-ns table 14: clock, data, strobe, and mask pins applies to dq0?dqxx, dqs, dqs#, rdqs, rdqs #, udqs, udqs#, ldqs, ldqs#, dm, udm, ldm parameter specification -3 -37e maximum peak amplitude allowed for overshoot area (see figure 22) 0.9v 0.9v maximum peak amplitude allowed for undershoot area (see figure 22) 0.9v 0.9v maximum overshoot area above v dd q (see figure 22) 0.38v-ns 0.28v-ns maximum undershoot area below v ss q (see figure 23) 0.38v-ns 0.28v-ns overshoot area maximum amplitude v dd / v dd q v ss/ v ss q volts time (ns) (v) undershoot area maximum amplitude v ss/ v ss q volts time (ns) (v)
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 27 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? output electrical characteris tics and operating conditions note: 1. the typical value of v ox (ac) is expected to be about 0.5 x v dd q of the transmitting device and v ox (ac) is expected to track variations in v dd q. v ox (ac) indicates the voltage at which di fferential output signals must cross. figure 24: differential output signal levels table 15: differential ac output parameters parameter symbol min max units notes ac differential cross-point voltage v ox ( ac ) 0.50 x v dd q - 125 0.50 x v dd q + 125 mv 1 ac differential voltage swing v swing 1.0 mv v tr v swing v cp v dd q v ss q v ox crossing point
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 28 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? note: 1. for i oh (dc); v dd q = 1.7v, v out = 1420mv. (v out - v dd q)/i oh must be less than 21 ? for values of v out between v dd q and v dd q - 280mv. 2. for i ol (dc); v dd q = 1.7v, v out = 280mv. v out /i ol must be less than 21 ? for values of v out between 0v and 280mv. 3. the dc value of v ref applied to the receiving device is set to v tt . 4. the values of i oh (dc) and i ol (dc) are based on the conditions given in note s 1 and 2. they are used to test device drive current capability to ensure v ih (min) plus a noise margin and v il (max) minus a noise marg in are delivered to an sstl_18 receiver. the actual current values are derived by sh ifting the desired driver oper ating point (see output iv curves) along a 21 ? load line to define a convenie nt driver current for measurement. note: 1. absolute specifications: 0c t case +85c ; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v. 2. impedance measurement condition for output source dc current: v dd q = 1.7v; v out = 1420mv; (v out - v dd q)/i oh must be less than 23.4 ? for values of v out between v dd q and v dd q - 280mv. impedance measurement condition for output sink dc current: v dd q = 1.7v; v out = 280mv; v out /i ol must be less than 23.4 ? for values of v out between 0v and 280mv. 3. mismatch is absolute value between pull-up and pull-dow n, both are measured at same temperature and voltage. 4. output slew rate for falling and rising edges is measured between v tt - 250mv and v tt + 250mv for single ended sig- nals. for differential signals (e.g. dqs - dqs#) output slew rate is measured between dqs - dqs# = -500mv and dqs# - dqs = +500mv. output slew rate is guaranteed by design, but is not ne cessarily tested on each device. 5. the absolute value of the slew rate as measured from v il (dc)max to v ih (dc) min is equal to or greater than the slew rate as measured from v il (ac) max to v ih (ac) min. this is guaranteed by design and characterization. figure 25: output slew rate load table 16: output dc current drive parameter symbol value units notes output minimum source dc current i oh -13.4 ma 1,3,4 output minimum sink dc current i ol 13.4 ma 2,3,4 table 17: output characteristics parameter symbol min nom max units notes output impedance 12.6 18 23.4 ? s 1,2 pull-up and pull -down mismatch 04 ? s 1,2,3 output slew rate 1.5 5 v/ns 1,4,5 output (v out ) reference point 25 ? v tt = v dd q/2
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 29 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? full strength pull-down driver characteristics figure 26: full strength pull-down characteristics pull-down characteristics 0.00 20.00 40.00 60.00 80.00 100.00 120.00 0.0 0.5 1.0 1.5 vout (v) iout (ma) table 18: pulldown current (ma) voltage (v) minimum nominal maximum 0.0 0.00 0.00 0.00 0.1 4.3 5.63 7.95 0.2 8.6 11.3 15.90 0.3 12.9 16.52 23.85 0.4 16.9 22.19 31.80 0.5 20.4 27.59 39.75 0.6 23.28 32.39 47.70 0.7 25.44 36.45 55.55 0.8 26.79 40.38 62.95 0.9 27.67 44.01 69.55 1.0 28.38 47.01 75.35 1.1 28.96 49.63 80.35 1.2 29.46 51.71 84.55 1.3 29.90 53.32 87.95 1.4 30.29 54.9 90.70 1.5 30.65 56.03 93.00 1.6 30.98 57.07 95.05 1.7 31.31 58.16 97.05 1.8 31.64 59.27 99.05 1.9 31.96 60.35 101.05
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 30 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? full strength pull-up driver characteristics figure 27: full streng th pull-up characteristics pull-up characteristics -120.0 -100.0 -80.0 -60.0 -40.0 -20.0 0.0 0.0 0.5 1.0 1.5 vddq - vout (v) iout (ma) table 19: pull-up current (ma) voltage (v) minimum nominal maximum 0.0 0.00 0.00 -0.00 0.1 -4.3 -5.63 -7.95 0.2 -8.6 -11.3 -15.90 0.3 -12.9 -16.52 -23.85 0.4 -16.9 -22.19 -31.80 0.5 -20.4 -27.59 -39.75 0.6 -23.28 -32.39 -47.70 0.7 -25.44 -36.45 -55.55 0.8 -26.79 -40.38 -62.95 0.9 -27.67 -44.01 -69.55 1.0 -28.38 -47.01 -75.35 1.1 -28.96 -49.63 -80.35 1.2 -29.46 -51.71 -84.55 1.3 -29.90 -53.32 -87.95 1.4 -30.29 -54.90 -90.70 1.5 -30.65 -56.03 -93.00 1.6 -30.98 -57.07 -95.05 1.7 -31.31 -58.16 -97.05 1.8 -31.64 -59.27 -99.05 1.9 -31.96 -60.35 -101.05
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 31 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? fbga package capacitance note: 1. this parameter is sampled. v dd = +1.8v 0.1v, v dd q = +1.8v 0.1v, v ref = v ss , f = 100 mhz, t case = 25c, v out (dc) = v dd q/2, v out (peak to peak) = 0.1v. dm input is grouped with i/o pins, reflecting the fact that they are matched in loading. 2. the input capacitance per pin group will not differ by more than this maximum amount for any given device. 3. the i/o capacitance per dqs and dq by te/group will not differ by more than this maximum amount for any given device. table 20: input capacitance parameter symbol min max units notes input capacitance: ck, ck# cck 1.0 2.0 pf 1 delta input capacitance: ck, ck# cdck ? 0.25 pf 2 input capacitance: ba1- ba0, a0-a12, cs#, ras#, cas#, we#, cke, odt ci 1.0 2.0 pf 1 delta input capacitance: ba1-ba0, a0-a12, cs#, ras#, cas#, we#, cke, odt cdi ? 0.25 pf 2 input/output capacitance: dqs, dqs, dm, nf cio 2.5 4.0 pf 1 delta input/output capaci tance: dqs, dqs, dm, nf cdio ? 0.5 pf 3
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 32 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? i dd specifications and conditions table 21: ddr2 i dd specifications and conditions notes: 1?5; notes appear on page 33. parameter/condition symbol config -3 -37e units operating one bank active-precharge current; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, cs# is high between valid comma nds; address bus inputs are switching; data bus inputs are switching. i dd 0 x4, x8 tbd 80 ma x16 tbd 80 operating one bank active-read-precharge current; iout = 0ma; bl = 4, cl = cl(i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid co mmands; address bus inputs are switching; data pattern is same as i dd 4w. i dd 1 x4, x8 tbd 90 ma x16 tbd 90 precharge power-down current ; all banks idle; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating. i dd 2p x4, x8, x16 tbd 5 ma precharge quiet standby current ; all banks idle; t ck = t ck (i dd ); cke is high, cs# is high; other control and address bus inputs are stable; data bus inputs are floating. i dd 2q x4, x8 tbd 35 ma x16 tbd 35 precharge standby current ; all banks idle; t ck = t ck (i dd ); cke is high, cs# is high; other control and address bus inputs ar e switching; data bus inputs are switching. i dd 2n x4, x8 tbd 35 ma x16 tbd 35 active power-down current ; all banks open; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating. i dd 3p fast pdn exit mr[12] = 0 tbd 25 ma slow pdn exit mr[12] = 1 tbd 6 active standby current ; all banks open; t ck = t ck(i dd ), t ras = t ras max (i dd ), t rp = t rp(i dd ); cke is high, cs# is high between valid commands; other control and address bus inputs are swi tching; data bus inputs are switching. i dd 3n x4, x8 tbd 40 ma x16 tbd 40 operating burst write current ; all banks open, continuous bur st writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid comma nds; address bus inputs are switching; data bus inputs are switching. i dd 4w x4, x8 tbd 160 ma x16 tbd 180 operating burst read current ; all banks open, continuous burst reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs ar e switching; data bu s inputs are switching. i dd 4r x4, x8 tbd 150 ma x16 tbd 160 burst refresh current ; t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval; cke is high, cs# is high between vali d commands; other control and address bus inputs are switching; data bus inputs are switching. i dd 5 x4, x8 tbd 170 ma x16 tbd 170 self refresh current ; ck and ck# at 0v; cke 0.2v; other control an d address bus inputs are floating; data bus inputs are floating. i dd 6 x4, x8, x16 tbd 5 ma
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 33 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? note: 1. i dd specifications are tested after the device is properly initialized. 0c t case 85c. v dd = +1.8v 0.1v, v dd q = +1.8v 0.1v, v dd l= +1.8v 0.1v, v ref = v dd q/2. 2. input slew rate is specified by ac parametric test conditions. 3. i dd parameters are specified with odt disabled. 4. data bus consists of dq, dm, dqs, dqs#, rdqs, rdqs#, ldqs, ldqs#, udqs, and udqs#. i dd values must be met with all combinations of emr bits 10 and 11. 5. definitions for i dd conditions: low is defined as v in v il (ac) (max). high is defined as v in v ih (ac) (min). stable is defined as inputs stable at a high or low level. floating is defined as inputs at v ref = v dd q/2. switching is defined as inputs changing between high and low every other clock cycle (once per two clocks) for address and control signals. switching is defined as inputs changing between high and low every other data transfer (once per clock) for dq signals not includ ing masks or strobes. operating bank interleave read current ; all bank interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd )-1 x t ck (i dd ); t ck = t ck (i dd ), t rc = t rc(i dd ), t rrd = t rrd(i dd ), t rcd = t rcd(i dd ); cke is high, cs# is high between valid commands; address bus inputs are stable during deselects; data bus inputs are switching; see i dd 7 conditions for detail. i dd 7 x4, x8 tbd 240 ma x16 tbd 240 table 21: ddr2 i dd specifications and conditions (continued) notes: 1?5; notes appear on page 33. parameter/condition symbol config -3 -37e units table 22: general i dd parameters i dd parameter -3 -37e units cl (i dd ) 54 t ck t rcd (i dd ) 15 15 ns t rc (i dd ) 60 60 ns t rrd (i dd ) - x4/x8 7.5 ns t rrd (i dd ) - x16 10 ns t ck (i dd ) 3.75 ns t ras min (i dd ) 15 45 ns t ras max (i dd ) 70,000 ns t rp (i dd ) 15 ns t rfc (i dd ) 127.5 ns
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 34 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? i dd 7 conditions the detailed timings are shown below for i dd 7. changes will be required if timing parameter changes are made to the specification. note: 1. legend: a = active; ra = read auto precharge; d = deselect. 2. all banks are being in terleaved at minimum t rc (i dd ) without violating t rrd (i dd ) using a burst length of 4. 3. control and address bus inputs are stable during deselects. 4. i out = 0ma. table 23: i dd 7 timing patterns all bank interleav e read operation speed grade i dd 7 timing patterns for x4/x8/x16 -3 a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d d d -37e a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d d d table 24: ac operating co nditions (sheet 1 of 4) notes: 1?5; notes appear on page 38; 0c t case +85c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics symbol -3 -37e units notes parameter min max min max clock clock cycle time cl = 4 t ck (4) 3,750 8,000 ps 16, 25 cl = 5 t ck (5) 3,000 8,000 ps 16, 25 ck high-level width t ch 0.45 0.55 0.45 0.55 t ck 19 ck low-level width t cl 0.45 0.55 0.45 0.55 t ck 19 half clock period t hp min ( t ch, t cl) min ( t ch, t cl) ps 20 clock jitter t jit tbd tbd tbd tbd ps 18
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 35 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? data dq output access time from ck/ck# t ac -600 +600 -500 +500 ps data-out high-imp edance window from ck/ck# t hz t ac max t ac max ps 8, 9 data-out low-imp edance window from ck/ck# t lz t ac min t ac max t ac min t ac max ps 8, 10 dq and dm input setup time relative to dqs t ds a 400 350 ps 7, 15, 22 dq and dm input ho ld time relative to dqs t dh a 400 350 ps 7, 15, 22 dq and dm input setup time relative to dqs t ds b 150 100 ps 7, 15, 22 dq and dm input ho ld time relative to dqs t dh b 275 225 ps 7, 15, 22 dq and dm input pulse width (for each input) t dipw 0.35 0.35 t ck data hold skew factor t qhs 450 400 ps dq?dqs hold, dqs to first dq to go nonvalid, per access t qh t hp - t qhs t hp - t qhs ps 15, 17 data valid output window (dvw) t dvw t qh - t dqsq t qh - t dqsq ns 15, 17 data strobe dqs input high pulse width t dqsh 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 t ck dqs output access time from ck/ck# t dqsck -500 +500 -450 +450 ps dqs falling edge to ck rising ? setup time t dss 0.2 0.2 t ck dqs falling edge from ck rising ? hold time t dsh 0.2 0.2 t ck dqs?dq skew, dqs to last dq valid, per group, per access t dqsq 350 300 ps 15, 17 dqs read preamble t rpre 0.9 1.1 0.9 1.1 t ck 36 dqs read postamble t rpst 0.4 0.6 0.4 0.6 t ck 36 dqs write preamble setup time t wpres 0 0 ps 12, 13 dqs write preamble t wpre 0.25 0.25 t ck dqs write postamble t wpst 0.4 0.6 0.4 0.6 t ck 11 write command to first dqs latching transition t dqss wl - 0.25 wl + 0.25 wl - 0.25 wl + 0.25 t ck table 24: ac operating co nditions (sheet 2 of 4) notes: 1?5; notes appear on page 38; 0c t case +85c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics symbol -3 -37e units notes parameter min max min max
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 36 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? command and address address and control input pulse width for each input t ipw 0.6 0.6 t ck address and control input setup time t is a 600 500 6, 22 address and control input hold time t ih a 600 500 6, 22 address and control input setup time t is b 350 250 6, 22 address and control input hold time t ih b 475 375 6, 22 cas# to cas# command delay t ccd 22 t ck active to active (same bank) command t rc 55 55 ns 34 active bank a to active bank b command t rrd (x4, x8) 7.5 7.5 ns 28 t rrd (x16) 10 10 ns 28 active to read or write delay t rcd 15 15 ns four bank activate period t faw (x4, x8) 37.5 37.5 ns 31 four bank activate period t faw (x16) 50 50 ns 31 active to precharge command t ras 40 70,000 40 70,000 ns 21, 34 internal read to precharge command delay t rtp 7.5 7.5 ns 24, 28 write recovery time t wr 15 15 ns 28 auto precharge write recovery + precharge time t dal t wr + t rp t wr + t rp ns 23 internal write to read command delay t wtr 10 7.5 ns 28 precharge command period t rp 15 15 ns 32 precharge all command period t rpa t rp + t ck t rp + t ck ns 32 load mode command cycle time t mrd 22 t ck cke low to ck,ck# uncertainty t delay 5.83 5.83 4.375 4.375 ns 29 refresh refresh to active or refresh to refresh command interval t rfc 75 70,000 75 70,000 ns 14 average periodic refresh interval t refi 7.8 7.8 s 14 self refresh exit self refresh to non-read command t xsnr t rfc (min) + 10 t rfc (min) + 10 ns exit self refresh to read command t xsrd 200 200 t ck exit self refresh timing reference t isxr 350 250 ps 6, 30 table 24: ac operating co nditions (sheet 3 of 4) notes: 1?5; notes appear on page 38; 0c t case +85c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics symbol -3 -37e units notes parameter min max min max
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 37 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? odt odt turn-on delay t aond 2222 t ck odt turn-on t aon t ac (min) t ac (max) + 1000 t ac (min) t ac (max) + 1,000 ps 26 odt turn-off delay t aofd 2.5 2.5 2.5 2.5 t ck odt turn-off t aof t ac (min) t ac (max) + 600 t ac (min) t ac (max) + 600 ps 27 odt turn-on (power-down mode) t aonpd t ac (min) + 2,000 2 x t ck + t ac (max) + 1000 t ac (min) + 2000 2 x t ck + t ac (max) + 1,000 ps odt turn-off (power-down mode) t aofpd t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 ps odt to power-down entry latency t anpd 33 t ck odt power-down exit latency t axpd 88 t ck power-down exit active power-down to read command, mr[bit12=0] t xard 22tck exit active power-down to read command, mr[bit12=1] t xards 6 - al 6 - al t ck exit precharge power-down to any non-read command. t xp 22 t ck exit precharge power-down to read command. t xprd 6 - al 6 - al t ck cke minimum high/low time t cke 33 t ck 35 table 24: ac operating co nditions (sheet 4 of 4) notes: 1?5; notes appear on page 38; 0c t case +85c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics symbol -3 -37e units notes parameter min max min max
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 38 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? notes 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical ac and dc characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device oper ation are guaranteed for the full voltage range specified. 3. outputs measured with equivalent load: 4. ac timing and i dd tests may use a v il -to-v ih swing of up to 1.0v in the test environment and parameter specifications are guaranteed for the specified ac input levels under normal use condi- tions. the minimum slew rate for the input sig- nals used to test the devi ce is 1.0v/ns for signals in the range between v il (ac) and v ih (ac). slew rates less than 1.0v/ns require the timing parame- ters to be derated as specified. 5. the ac and dc input level specifications are as defined in the sstl_18 standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above [below] the dc input low [high] level). 6. command/address minimum input slew rate is at 1.0v/ns. command/address input timing must be derated if the slew rate is not 1.0v/ns. this is easily accommodated using t is b and the setup and hold time derating values table. t is timing ( t is b ) is referenced from v ih ( ac ) for a rising signal and v il ( ac ) for a falling signal. t ih timing ( t ih b ) is refer- enced from v ih ( ac ) for a rising signal and v il ( dc ) for a falling signal. the timing table also lists the t is b and t ih b values for a 1.0v/n s slew rate; these are the ?base? values. 7. data minimum input slew rate is at 1.0v/ns. data input timing must be derated if the slew rate is not 1.0v/ns. this is easily accommodated if the tim- ing is referenced from the logic trip points. t ds timing ( t ds b ) is referenced from v ih (ac) for a ris- ing signal and v il (ac) for a falling signal. t ih tim- ing ( t ih b ) is referenced from v ih (dc) for a rising signal and v il ( dc ) for a falling signal. the timing table lists the t ds b and t dh b values for a 1.0v/ns slew rate. if the dqs/dqs# differential strobe feature is not enabled, timing is no longer referenced to the crosspoint of dqs/dqs#. data timing is now ref- erenced to v ref , provided the dqs slew rate is not less than 1.0v/ns. if the dqs slew rate is less than 1.0v/ns, then data timing is now referenced to v ih ( ac ) for a rising dqs and v il ( dc ) for a falling dqs. 8. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referenc ed to a specific volt- age level, but specify when the device output is no longer driving ( t hz) or begins driving ( t lz). 9. this maximum value is derived from the refer- enced test load. t hz (max) will prevail over t dqsck (max) + t rpst (max) condition. 10. t lz (min) will prevail over a t dqsck (min) + t rpre (max) condition. 11. the intent of the don?t care state after comple- tion of the postamble is the dqs-driven signal should either be high, low or high-z and that any signal transition within the input switching region must follow valid input requirements. that is if dqs transitions high (above v ih dc(min) then it must not transition low (below v ih (dc) prior to t dqsh(min). 12. this is not a device limit. the device will operate with a negative value, but system performance could be degraded due to bus turnaround. 13. it is recommended that dqs be valid (high or low) on or before the write command. the case shown (dqs going from high-z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss. 14. the refresh period is 64ms. this equates to an average refresh rate of 7.8125s. however, a refresh command must be asserted at least once every 70.3s or t rfc (max). to ensure all rows of all banks are properly refreshed, 8192 refresh commands must be issued every 64ms. 15. referenced to each output group: x4 = dqs with dq0?dq3; x8 = dqs with dq0?dq7; x16 = ldqs with dq0?dq7; and udqs with dq8?dq15. 16. ck and ck# input slew rate must be 1v/ns ( 2 v/ns if measured differentially). output (v out ) reference point 25 ? v tt = v dd q/2
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 39 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? 17. the data valid window is derived by achieving other specifications - t hp. ( t ck/2), t dqsq, and t qh( t qh = t hp - t qhs). the data valid window derates in direct proportion to the clock duty cycle and a practical data valid window can be derived. 18. t jit specification is currently tbd. 19. min( t cl, t ch) refers to the smaller of the actual clock low time and the ac tual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch). for example, t cl and t ch are = 50 percent of the period, less the half period jitter [ t jit(hp)] of the clock source, and less the half period jitter due to cross talk [ t jit(cross talk)] into the clock traces. 20. t hp (min) is the lesser of t cl minimum and t ch minimum actually applied to the device ck and ck# inputs. 21. reads and writes with auto precharge are allowed to be issued before t ras (min) is satisfied since t ras lockout feature is supported in ddr2 sdram. 22. v il /v ih ddr2 overshoot/undershoot. see ?ac overshoot/undershoot spec ification? on page 74. 23. t dal = (nwr) + ( t rp/ t ck): for each of the terms above, if not already an integer, round to the next highest integer. t ck refers to the application clock period; nwr refers to the t wr parameter stored in the mr[11,10,9]. example: for -37e at t ck = 3.75 ns with t wr programmed to four clocks. t dal = 4 + (15 ns/3.75 ns) clocks = 4 +(4) clocks = 8 clocks. 24. the minimum read to internal precharge time. this parameter is only applicable when t rtp/(2* t ck) > 1. if t rtp/(2* t ck) 1, then equa- tion al + bl/2 applies. notwithstanding, t ras (min) has to be satisfied as well. the ddr2 sdram will automatically delay the internal pre- charge command until t ras (min) has been satisfied. 25. operating frequency is only allowed to change during self refresh mode (see ?self refresh? on page 28), precharge power-down mode (see ?power-down mode? on page 31), and system reset condition (see ?reset function (cke low anytime)? on page 2. 26. odt turn-on time t aon (min) is when the device leaves high impedance and odt resistance begins to turn on. odt turn-on time t aon (max) is when the odt resistance is fully on. both are measured from t aond. 27. odt turn-off time t aof (min) is when the device starts to turn off odt resistance. odt turn off time t aof (max) is when the bus is in high impedance. both are measured from t aofd. 28. this parameter has a two clock minimum require- ment at any t ck. 29. t delay is calculated from t is + t ck + t ih so that cke registration low is guaranteed prior to ck, ck# being removed in a system reset condition. ?reset function (cke low anytime)? on page 2. 30. t isxr is equal to t is and is used for cke setup time during self refresh exit shown in figure 31 on page 30. 31. no more than 4 bank active commands may be issued in a given t faw(min) period. t rrd(min) restriction still applies. the t faw(min) parameter applies to all 8 bank ddr2 devices, regardless of the number of banks al ready open or closed. 32. trpa timing applies when the precharge(all) command is issued, regardless of the number of banks already open or cl osed. if a single-bank precharge command is issued, t rp timing applies. t rpa(min) applies to all 8-bank ddr2 devices. 33. value is minimum pulse width, not the number of clock registrations. 34. applicable to read cycles only. write cycles gen- erally require additional time due to write recov- ery time ( t wr) during auto precharge. 35. t cke (min) of 3 clocks means cke must be regis- tered on three consecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the 3 clocks of regis- tration. thus, after any cke transition, cke may not transition from its valid level during the time period of t is + 2 * t ck + t ih. 36. this parameter is not referenced to a specific volt- age level, but specified whwen the device output is no longer driving ( t rpst) or beginning to drive ( t rpre).
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 40 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? figure 28: package drawin g 60-ball (8mm x 12mm) fbga note: all dimensions ar e in millimeters. ball a1 id 1.3 max mold compound: epoxy novolac substrate: plastic laminate solder ball material: 62% sn, 36% pb, 2% ag or 95.5% sn, 3% ag, 0.5% cu solder ball pad: ? .33mm ball a9 0.80 typ 8.00 0.10 4.00 0.05 3.20 0.05 4.00 0.05 0.850 0.05 0.155 0.013 seating plane c 8.00 6.40 1.80 0.05 ctr 0.10 c 60x ? 0.45 solder ball diameter refers to post reflow condition. the pre- reflow diameter is ? 0.42 c l 12.00 0.10 ball a1 ball a1 id 0.80 typ 6.00 0.05 c l
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 41 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? figure 29: package drawin g 84-ball (8mm x 14mm) fbga note: all dimensions ar e in millimeters. data sheet designation no mark: this data sheet co ntains minimum and maximum limits specified over the complete power supply and temperature range for production devices. although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. ball #1 id seating plane 0.850 0.05 1.80 0.05 ctr 0.155 0.013 0.10 c c 1.3 max mold compound: epoxy novolac substrate: plastic laminate solder ball material: 62% sn, 36% pb, 2% ag or 96.5% sn, 3% ag, 0.5% cu solder ball pad: ? 0.33mm c l c l 3.20 0.05 4.00 0.05 8.00 0.10 ball a1 id 11.20 5.60 0.05 ball a9 ball a1 solder ball diameter refers to post reflow condition. the pre- reflow diameter is ?0.42 84x ?0.45 14.00 0.10 7.00 0.05 0.80 typ 0.80 typ 6.40
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 42 ?2003 micron technology, inc. all rights reserved. 900 e. karcher rd. nampa, id 83687 e-mail: sales@spectek_info@spectek.com, internet: http://www.spectek@spectek.com spectek, the s logo, and the spectek logo are trademarks of micron technology, inc. disclaimer: except as specifically provided in this document, spectek makes no warranties, expressed or implied, including, but not limited to, any implied warranties of merchantability or fitness for a particular purpose. any claim against spectek must be made within 1 year from the dat e of shipment from spectek, and spectek has no liability there after. any liability is limited to replacement of the defective items or return of amounts paid for defective items (at buyer?s electi on). in no event will spectek be responsible for special, indire ct, consequential or incidental damages, even if spectek has been advised for the pos sibility of such damages. spectek?s liability from any cause pursuant to this specification shall be limited to general monetary damages in an a mount not to exceed the total purchase price of the products cove red by this specification, regardless of the form in which legal or equitable action may be brought against spectek. 256mb: x4, x8, x16 ddr2 sdram ? ? part number options and designations prior to march 2005 part number options and designations prior to july 2006 options designation spectek ddr2 family saaux6x (call spectek sales for details on availability of ?x? placeholders) voltage 1.8v 0 1.9v a refresh 8k refresh 8 configuration 64 meg x 4 (16 meg x 4 x 4) 64m4 32 meg x 8 ( 8 meg x 8 x 4) 32m8 16 meg x 16 (4 meg x 16 x 4) 16m16 fbga package lead-free x4, x8 60-ball fbga (8mm x 12mm) fi x16 84-ball fbga (8mm x 14mm) fp timing ? cycle time 3.0ns @ cl = 5 (ddr2-667) -3 3.75ns @ cl = 4 (ddr2-533) -37e options designation spectek memory saa configuration 64 meg x 4 (16 meg x 4 x 4) 64m4 32 meg x 8 ( 8 meg x 8 x 4) 32m8 16 meg x 16 (4 meg x 16 x 4) 16m16 product code ddr2 ux density 256 megabits 6x voltage/refresh 1.8v/8k refresh o8 package ? lead-free x4, x8 60-ball fbga (8mm x 12mm) fif x16 84-ball fbga (8mm x 14mm) fpf package ? leaded x4, x8 60-ball fbga (8mm x 12mm) fil x16 84-ball fbga (8mm x 14mm) fpl timing ? cycle time 3.0ns @ cl = 5 (ddr2-667) -3 3.75ns @ cl = 4 (ddr2-533) -37e
pdf: 09005aef81548c1c/source: 09005aef819e80c5 spectek reserves the right to change products or specifications without notice. spectek_ddr2_256mb_2.fm - rev. c 7/06 en 43 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ? revision history rev. c, pub. 07/06 updated part number on page 1. added leaded and lead-fre e designators on page 1. rev. b, pub. 3/05 updated options/designations on page 1. moved options/designations prior to 3/04 to page 42. added web link to page 5. rev. a, preliminary, pub. 10/04 original publication

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